Method for image reversal of implant resist using a single photolithography exposure and structures formed thereby

ABSTRACT

A method for image reversal in semiconductor processing includes forming a first implant mask layer upon a semi-conductor substrate and forming a patterned photoresist layer over the first implant mask layer. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-patterned portions of the substrate. The photoresist layer is then removed, and a second implant mask layer is formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional application of U.S. Ser. No.10/604,009, filed Jun. 20, 2003, the contents of which are incorporatedby reference herein in their entirety.

BACKGROUND OF INVENTION

[0002] The present invention relates generally to semiconductor devicemanufacturing and, more particularly, to a method for image reversal ofimplant resist using a single photolithography exposure and structuresformed thereby.

[0003] The manufacturing of semiconductor devices is dependent upon theaccurate replication of computer aided design (CAD) generated patternsonto the surface of a device substrate. The replication process istypically performed using lithographic processes, followed by a varietyof subtractive (etch) and additive (deposition) processes. Moreparticularly, a photolithography process typically includes applying alayer of a photoresist material (i.e., a material that will react whenexposed to light), and then selectively exposing portions of thephotoresist to light or other ionizing radiation (e.g., ultraviolet,electron beams, X-rays, etc.), thereby changing the solubility ofportions of the material. The resist is then developed by washing itwith a basic developer solution, such as tetramethylammonium hydroxide(TMAH), thereby removing the non-irradiated (in a negative resist) orirradiated (in a positive resist) portions of the resist layer.

[0004] In the fabrication of complementary metal oxide semiconductor(CMOS) devices, several implant masks are used to form appropriatesource and drain areas on the chip. For p-type and n-type CMOS devices(e.g., NFETs, PFETs), some of these patterns are complementary; that is,the pattern used for creating the p-type devices is the reverse of thepattern used for creating the n-type devices. More specifically, twoseparate masks are used in CMOS device processing in which either apositive or negative resist is used to carry out two separate,complementary masking and implanting steps. For example, a first implantpattern is formed by creating a first patterned (positive or negative)photoresist layer over a substrate. A first ion implantation step isused to implant the exposed areas of the substrate with a first dopantmaterial (e.g., a p-type material). Subsequently, the first patternedlayer is stripped and a second patterned resist (of the same tone as thefirst resist) is used to expose the complementary regions of thesubstrate regions in order to carry out the complementary implantationwith a second dopant material (e.g., an n-type material).

[0005] However, as devices become even more miniaturized over time, theconventional methods for complementary device implantation are moresusceptible to alignment errors as a result of the separate maskingsteps. Such alignment errors would limit the density and performance ofthe resulting devices. These alignment errors may include rotationerrors, translation errors, overlap errors, and/or image sizedeviations. In turn, the possibility of incurring one or more of theseerrors results in the increase of the overall device error placementbudget, thereby reducing valuable chip real estate that would otherwisebe used for additional devices.

[0006] An image reversal process is another known technique used in CMOSdevice processing, in which a combination of positive and negativeresists is used for such steps as gate/line patterning or contact holepatterning. In one approach, a positive photoresist layer formed over asubstrate is patterned to create an opening for a gate pattern or a linepattern. Subsequently, a negative resist is formed over the irradiatedpositive photoresist, including the formed opening. Then, the negativeresist is recessed such that it remains only in the area defined by theopening formed in the positive resist layer, while the remainingpositive resist is removed. The remaining hardened negative resistdefines the location for the gate or line pattern.

[0007] Although this type of image reversal process may be used to formcertain types of semiconductor structures, it is not particularly suitedfor the type of complementary implant regions discussed above, due tointermixing between negative and positive photoresists during apply. Theintermixing will cause deformation of the underlying first resistpattern, impacting linewidth control and causing residual resistdefects. Moreover, even if this approach were able to be adapted forcomplementary device implantation, there are still two separatelithography steps needed in accomplishing the image reversal. Anotherexisting approach is to utilize spun-on glass (SOG) over photoresist forimage reversal purposes. However, SOG is an oxide material that istypically removed using harsh solvents such as dilute HF or buffered HF,and which in turn tends to cause damage to the other oxide layers on thedevice substrate.

[0008] Unfortunately, a significant part of the cost of an integratedcircuit chip is contained in the lithography processes used to patternthese implant mask levels. As such, it would be desirable to be able toimplement image reversing for applications such as CMOS deviceimplantation, but without the added lithography step used heretofore (orthe added risk of device damage in removing SOG) to accomplish the imagereversal.

SUMMARY OF INVENTION

[0009] The foregoing discussed drawbacks and deficiencies of the priorart are overcome or alleviated by a method for image reversal insemiconductor processing. In an exemplary embodiment, the methodincludes forming a first implant mask layer upon a semiconductorsubstrate and forming a patterned photoresist layer over the firstimplant mask layer. Portions of the first implant mask layer not coveredby the patterned photoresist layer are removed so as to exposenon-patterned portions of the substrate. The photoresist layer is thenremoved, and a second implant mask layer is formed over thenon-patterned portions of the substrate, wherein the first implant masklayer has an etch selectivity with respect to the second implant masklayer. The remaining portions of the first implant mask layer areremoved to expose a reverse image of the substrate, including initiallypatterned portions of the substrate.

[0010] In another aspect, a method for implementing image reversal forsemiconductor device implantation includes forming a first implant masklayer upon a semiconductor substrate and forming a patterned photoresistlayer over the first implant mask. Portions of the first implant masklayer not covered by the patterned photoresist layer are removed so asto expose non-patterned portions of the substrate. The photoresist layeris removed, and the exposed, non-patterned portions of the substrate aresubjected to a first implantation. A second implant mask layer is thenformed over the non-patterned portions of the substrate, wherein thefirst implant mask layer has an etch selectivity with respect to thesecond implant mask layer. The remaining portions of the first implantmask layer are removed to expose a reverse image of the substrate,including initially patterned portions of the substrate. The exposedinitially patterned portions of the substrate are then subjected to asecond implantation.

[0011] In still another aspect, a semiconductor device has a firstimplant region having a first conductivity type and a second implantregion having a second conductivity type, wherein the first and saidsecond implant regions are self-aligned with respect to one another.

BRIEF DESCRIPTION OF DRAWINGS

[0012] Referring to the exemplary drawings wherein like elements arenumbered alike in the several Figures:

[0013] FIGS. 1(a)-1(h) illustrate a method for image reversal of animplant resist, in accordance with an embodiment of the invention; and

[0014] FIGS. 2(a)-2(d) illustrates examples of semiconductor deviceswith complementary implant regions having one or more alignment errorsassociated therewith; and

[0015] FIGS. 3(a) and 3(b) illustrate a semiconductor device havingself-aligned, complementary implant regions formed using the methods ofFIGS. 1(a)-1(h), in accordance with a further embodiment of theinvention.

DETAILED DESCRIPTION

[0016] Disclosed herein is a non-lithographic process used to reversethe tone of an implant pattern formed on a semi-conductor substrate,thereby allowing a single lithography exposure to serve as a templatefor two different implant masking steps. This process, in turn, may beutilized to form semiconductor devices (such as CMOS devices) havingself-aligned, complementary implant regions that allow for tighteralignment tolerances and greater chip real estate savings.

[0017] Referring generally to FIGS. 1(a)-1(h), there is shown a methodfor image reversal in semiconductor processing, in accordance with anembodiment of the invention. In particular, FIG. 1(a) illustrates asemiconductor substrate 100, such as silicon. It will be noted that thesubstrate 100 is intended to include other features (not shown forpurposes of clarity), such as a shallow trench isolation region (STI),silicon-on-insulator (SOI), SiGe structures, and the like. The substrate100 is coated with an optional etch stop layer (e.g., a thin layer oforganic antireflective coating (ARC)) 102 thereupon, followed by a firstimplant mask layer 104 (e.g., of silicon ARC (Si-ARC), which iscommercially available, for example, from Shin-Etsu). Additional detailsregarding Si-ARC may be found in U.S. patent application Ser. No.10/124,087, filed Apr. 16, 2002 (and assigned to the assignee of thepresent application), the contents of which are incorporated herein byreference in their entirety.

[0018] The first implant mask layer 104 is chosen to be thick enough andto have sufficient stopping power to stop a subsequent implant fromentering the substrate 100. Suitable materials for the first implantmask layer 104 should have good selectivity (i.e., a higher etch rate)relative to an overlying resist layer and the underlying etch stop layer102. Etch processes for the implant mask layer 104, such as fluorine orfluorine/oxygen mixture plasmas, tend to damage the substrate surface.Therefore, the etch stop layer 102 is provided directly on the substratesurface 100 to provide protection for the substrate surface during theetch of the implant mask layer (e.g., Si-ARC) 104.

[0019] During the patterned etch of the first implant mask layer 104,the etch stop layer 102 should etch at a significantly slower rate thanthe first implant mask layer 104. Thus, one suitable etch stop layer 102may be an organic polymer like the deep ultraviolet (DUV) ARC, such asthose made available from Brewer Science or Shipley. For example, anorganic ARC for 193 nanometer (nm) lithography, such as that supplied byShipley, would be applied at a thickness in the range of from about 40nm to about 100 nm, depending on the thickness of the overlying implantmask layer 104 and the selectivity of the etch process. In thisembodiment, Si-ARC is a suitable implant mask layer material, which maybe applied at a thickness of about 150 nm to about 400 nm, and morepreferably at about 190 nm.

[0020] Then, a photoresist layer, which may include any resist that hasa good etch rate relative to the first implant mask layer 104 (e.g., theSi-ARC layer in the illustrated embodiment), is applied over the firstmask implant layer 104 using standard post-apply and post-expose bakesas recommended by the supplier. The thickness of the resist layer 106 ispreferably in the range of about 50-300 nm, and more preferably fromabout 120-160 nm. Thereafter, the resist layer is lithographicallypatterned and exposed. The remaining patterned resist 106 is shown inFIG. 1(a).

[0021] Next, as illustrated in FIG. 1(b), the exposed areas of theimplant mask (e.g., Si-ARC) layer 104 are removed through etching in aplasma reactive ion etch (RIE), such as, but not limited to, a fluorineplasma or fluorine/oxygen plasma, as well known in the art. Theselectivity of the etch of the first implant mask layer 104 relative tothe patterned resist layer 106 is high, wherein (for example) only about20 nm of resist 106 is consumed while the exposed areas of the implantmask layer 104 is preferably completely consumed. If the optionalorganic ARC layer 102 is used, then the etch is terminated thereupon soas to avoid damage to the substrate 100. The organic ARC layer 102 maythen be removed with a brief RIE process, for example using mixtures ofoxygen, argon, nitrogen, or more preferably O₂, during which theremaining resist layer 106 over the patterned etch stop layer 102 (e.g.,Si-ARC) may also be removed.

[0022] At this point, the patterned substrate 100 is ready for a firstimplantation process. Thus, for example, in CMOS device processing, adopant material(s) (e.g., arsenic, boron, phosphorous, etc.) may beimplanted by standard techniques. An angled implant may be performed atsome angle with respect to the substrate surface or, as shown in FIG.1(c), the implant may be orthogonal to the substrate 100. This resultsin a first implant region 107, as illustrated in FIG. 1(d).

[0023] Once the first implant region 107 is complete, the substrate 100is then ready for the image reversal process, which will allow a secondimplant to be performed for the complementary substrate areas previouslyprotected by the first implant mask (e.g., Si-ARC) layer 104. Priorthereto, the first implant mask Si-ARC layer 104 (and any remainingresist material thereon) may be ultraviolet (UV) hardened. As shown inFIG. 1(d), a second implant mask layer 108 is applied over thesubstrate. The second implant mask layer 108 may be a polyimide that iscompatible with CMP processing and has a low etch rate relative to thefirst implant mask layer 104. Other suitable materials for the secondimplant mask layer 108 include organic ARC materials, such as the ARCused for the etch stop layer 102. Such an organic film may be spinapplied to the substrate and over the existing patterned first implantmask layer 104, and may further be thermally crosslinked so as to hardenthe second implant mask layer 108 for subsequent chemical mechanicalpolishing (CMP) processes.

[0024] The second implant mask layer (e.g., an organic film layer) 108,is preferably applied to cover the first implant mask layer 104, forexample at a thickness in the range of about 200 to about 450 nm. Afterthe spin on application, the organic layer 108 is thermally cured bybaking and is thereby cross-linked. Then, as shown in FIG. 1(e), theexcess portions of second implant mask layer (e.g., the cross-linkedorganic layer) 108 are removed (by CMP, for example) so as to expose thetop surface of the first implant mask (e.g., Si-ARC) layer 104.

[0025] In FIG. 1(f), the initially patterned Si-ARC layer 104 is thenremoved using the same or similar fluorine plasma RIE process used inremoving the unpatterned Si-ARC areas, using a RIE process that etchesthe first implant mask layer 104 preferably to the second implant mask(e.g., organic film) layer 108, thereby leaving most of the organic ARCfilm layer 108 in place. For example, after polishing and etching, theremay be about 100-350 nm of the second implant mask layer 108 (e.g.,organic ARC) remaining on the bulk of the substrate surface. Forexample, in FIG. 1(g), the exposed protective etch stop layer (e.g.,organic ARC) 102 has been removed with an oxygen RIE, as in the initialimplant process described above. At this point, there may be about50-300 nm of the second implant mask layer (e.g., organic ARC) remainingto serve as a mask for the complementary implant, which forms the secondimplant region 109, as also illustrated in FIG. 1(g). The second implantregion 109 may be different from the first implant region 107. Finally,as shown in FIG. 1(h), the remaining organic ARC mask layer 108 isstripped, leaving the substrate 100 with the completed, complementarydopant implant regions 107, 109.

[0026] For N-well and P-well structures, relatively deeper implants arerequired, for example, up to about 1-2 microns, so that the thicknessesfor the etch stop 102, the first implant mask 104, and the resist layer106 would be thicker in order to block the deeper implants in regionswhere implants are not desired. The second implant mask layer 108 wouldalso be correspondingly thicker for such structures.

[0027] Depending on the particular application of the single lithographyimage reversal process, other materials may be substituted and/oromitted for one or more of the process steps described above. Forexample, if the desired implant patterns are all relatively narrow(e.g., having a height to width aspect ratio of about 2:1 or more), itmight be possible to avoid a CMP step and use a resist develop processto remove the second organic ARC masking layer 108 from the top of thefirst implant mask 104 Si-ARC patterns. This is possible because forhigh aspect ratio features, the spin-on layer 108 would tend to bethinner on top of the high aspect ratio features 104 than within thegaps. For example, a developable ARC could be applied to the substrateto form the second implant masking layer 108, and could be removed fromthe top of the first implant mask layer 104 by a developer solution, asillustrated in FIG. 1(e).

[0028] In addition to Si-ARC, it is also contemplated that other hardmask materials (such as silicon oxide, SOG, silicon nitride, SiGeoxide/nitride, at about 100 nm in thickness) may be substituted for thefirst implant mask layer 104. Generally, however, such materials aresomewhat less desirable due to a lower etch selectivity with respect toresist and ARC materials.

[0029] Furthermore, in addition to reducing the cost associated with anadditional lithography step, the present image reversal process may beused to form self-aligned masks and thus self-aligned semiconductordevices with complementary implant regions. FIGS. 2(a)-2(e) illustrateexamples of devices featuring butted junctions (i.e., adjacentlydisposed n-well and p-well regions) having one or more alignment errorsassociated therewith. For example, FIGS. 2(a) and 2(b) are a top viewand side cross-sectional view, respectively, of a conventionally formeddevice 200 wherein an N+ region 202 and P+ region 204 overlap oneanother at region 206. This misalignment has the undesired effect oflowering the device breakdown voltage.

[0030]FIG. 2(c) illustrates an alignment rotation error with respect toN+ region 202 and P+ region 204, while FIG. 2(d) illustrates analignment translation error in addition to an overlap error. Stillanother example is shown in FIG. 2(e), which illustrates an image sizedeviation of the P+ region 204, as well as translation and overlaperrors.

[0031] Accordingly, FIGS. 3(a) and 3(b) illustrate an exemplarysemiconductor device 300 having self-aligned, complementary implantregions, in accordance with a further aspect of the present invention.As can be seen, the use of the image reversal process described aboveallows for a tightly controlled offset between different implantregions, which has the desired effect of controlling the breakdownvoltage of the device 300, especially for butted junction devices. Thisin turn reduces the overall error placement budget, saving additionalvaluable chip real estate for additional devices.

[0032] While the invention has been described with reference to apreferred embodiment or embodiments, it will be understood by thoseskilled in the art that various changes may be made and equivalents maybe substituted for elements thereof without departing from the scope ofthe invention. In addition, many modifications may be made to adapt aparticular situation or material to the teachings of the inventionwithout departing from the essential scope thereof. Therefore, it isintended that the invention not be limited to the particular embodimentdisclosed as the best mode contemplated for carrying out this invention,but that the invention will include all embodiments falling within thescope of the appended claims.

1. A semiconductor device, comprising: a first implant region having a first conductivity type; and a second implant region having a second conductivity type; wherein said first and said second implant regions are self-aligned with respect to one another.
 2. The semiconductor device of claim 1, wherein said first implant region is formed following a lithographic patterning step and said second implant region is formed following a non-lithographic, image reversal step. 